Enhancing VLSI Designs with Logic Optimization Using Yosys

In the world of VLSI design, optimizing the logic of your circuits can significantly impact the overall performance and area efficiency of your chips. Yosys, an open-source synthesis tool, offers a powerful platform to perform such optimizations. In this blog post, we will explore how to use Yosys for logic optimization, specifically focusing on resource sharing, which is a critical technique for reducing the area of your designs.

Introduction to Logic Optimization

Logic optimization is a crucial step in the VLSI design flow. It involves refining your digital circuits to make them more efficient in terms of area, speed, and power consumption. Resource sharing, one of the key optimization strategies, reduces the number of resources — like multipliers or adders — used in a circuit by reusing them for different computations.

In this post, we will walk through a practical example of logic optimization using Yosys, demonstrating how resource sharing can lead to significant area savings in your designs.

Setting Up Yosys

Before diving into the optimization process, ensure that Yosys is installed on your system. If you haven’t installed Yosys yet, you can follow the installation steps detailed in a previous tutorial on Yosys. Additionally, you will need the following files for this tutorial:

• Design File: top.v

module top(clk, a, b, x, y, sel, z);
    input clk;
    input [7:0] a, b, x, y;
    input sel;
    output reg [15:0] z;

    always @(posedge clk) begin
        if (sel == 1'b0)
            z = a * b;
        else
            z = x * y;
    end
endmodule

• Unoptimized Script: top_opt.tcl

# read modules from Verilog file
read_verilog top.v
# translate processes to netlists
proc
# remove unused cells and wires
clean

# show the generic netlist
show

# mapping to internal cell library
techmap
# mapping flip-flops to toy.lib
dfflibmap -liberty NangateOpenCellLibrary_typical.lib
# mapping logic to toy.lib
abc -liberty NangateOpenCellLibrary_typical.lib
# remove unused cells and wires
clean

# report design statistics
stat -liberty NangateOpenCellLibrary_typical.lib

# Write the current design to a Verilog file
write_verilog -noattr -noexpr -nohex -nodec netlist_final_unopt.v

• Optimization Script: opt.tcl

# read modules from Verilog file
read_verilog top.v
# translate processes to netlists
proc
# remove unused cells and wires
clean

# show the generic netlist
show

# perform optimization
opt
# resource sharing optimization
share -aggressive

# show the generic netlist
show

# mapping to internal cell library
techmap
# mapping flip-flops to toy.lib
dfflibmap -liberty NangateOpenCellLibrary_typical.lib
# mapping logic to toy.lib
abc -liberty NangateOpenCellLibrary_typical.lib
# remove unused cells and wires
clean

# report design statistics
stat -liberty NangateOpenCellLibrary_typical.lib

# Write the current design to a Verilog file
write_verilog -noattr -noexpr -nohex -nodec netlist_final_opt.v

• Technology Library: NangateOpenCellLibrary_typical.lib

These files are essential for running the optimization process.

Understanding Resource Sharing

Resource sharing is a technique where the same hardware resource is used for multiple computations to save area. Let’s consider a simple example:

Suppose you have an RTL construct where:

• If select is 0, Z is assigned the value of A * B.
• If select is 1, Z is assigned the value of X * Y.

A direct implementation of this construct would require two multipliers, which consume significant area. However, by sharing the multiplier resource, we can reduce this to a single multiplier, controlled by a multiplexer.

Running the Optimization

Let’s run through the steps to see how Yosys handles this optimization:

1. Load the Design:

• Open Yosys by typing yosys in your terminal.
• Load the design file top.v into Yosys and run the initial synthesis commands. If you skip optimization, the tool will create a design with two multipliers.

2. Check the Unoptimized Design:

• Run the show command in Yosys to visualize the design. You should see two multipliers, each handling one of the multiplication operations.
• The area of this unoptimized design is reported as approximately 2,027 units.

Unoptimized Design

Chip Area before Optimization

Netlist file before Optimization (netlist_final_unopt.v)

3. Apply Resource Sharing Optimization:

• Now, let’s apply the resource sharing optimization by running the opt.tcl script in Yosys. This script includes commands that enable the tool to detect and optimize the resource-sharing opportunities.
• After running the script, Yosys will transform the design to use a single multiplier, controlled by a multiplexer.

Resource Sharing Optimization

4. Examine the Optimized Design:

• Visualize the optimized design using the show command again. You should now see only one multiplier in the design.
• The area of the optimized design is significantly reduced to approximately 1,169 units, demonstrating the effectiveness of resource sharing.

Optimized Design

Chip Area After Optimization

5. Generate the Final Netlist:

Finally, generate the Verilog netlist of the optimized design. The resulting netlist will be smaller in size compared to the unoptimized version, confirming that fewer gates and resources are being used.

Netlist file after Optimization (netlist_final_opt.v)

This tutorial highlights the power of logic optimization in VLSI design, particularly through the use of resource sharing. By using Yosys, you can easily implement such optimizations to make your designs more area-efficient. Whether you’re working on academic projects or professional VLSI design, Yosys provides a versatile tool set to help you achieve optimal results.

I encourage you to experiment further with Yosys and explore other optimization strategies to enhance your VLSI designs. Happy optimizing!