Exploring Logic Synthesis with Yosys: A Tutorial Overview

In the evolving world of VLSI design, the journey from RTL (Register-Transfer Level) to GDS (Graphic Data System) is both intricate and fascinating. As part of our recent exploration into this field, we delved into the practical aspects of logic synthesis using the open-source tool, Yosys Open Synthesis Suite.

Introduction to Yosys

Yosys is an open-source tool designed for performing RTL synthesis. It supports a variety of input formats, including Verilog, and can output synthesized netlists in several formats. In our tutorial, we utilized Yosys to synthesize a simple digital design and map it to a standard cell library.

Getting Started with Yosys

To begin with Yosys, ensure you have a Linux distribution installed on your system. Ubuntu is a popular choice, and it’s what we used in our demonstration. The installation process involves several dependencies, which you can easily install via the terminal. After setting up the environment, we cloned the Yosys repository from GitHub and compiled the source code.

Installation Commands:

$ sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys
$ make
$ sudo make install

Once installed, you can launch Yosys by simply typing ./yosys in the terminal.

Using Yosys for Logic Synthesis

In the session, we demonstrated the synthesis process using a simple Verilog design stored in a file named top.v. This design included basic combinational and sequential logic elements. We also used a technology library file from the Silvaco Open-Cell 45 nanometer free PDK libraries.

Verilog file and TCL Script:

/* Verilog code to demonstrate the netlist synthesis */

module top(a, b, clk, select, out);
    input a, b, clk, select;
    output out;
    reg out;
    wire y;

    assign y = (select) ? b : a;
    always @(posedge clk)
    begin
        out <= y;
    end
endmodule

# Read modules from Verilog file
read_verilog top.v

# Elaborate design hierarchy
hierarchy -check -top top

# Translate processes to netlists
proc

# Mapping to the internal cell library
techmap

# Mapping flip-flops to NangateOpenCellLibrary_typical.lib
# for e.g., always block
# Change the library file accordingly
dfflibmap -liberty NangateOpenCellLibrary_typical.lib

# Mapping logic to NangateOpenCellLibrary_typical.lib
# for e.g., assign block
abc -liberty NangateOpenCellLibrary_typical.lib

# Remove unused cells and wires
clean

# Write the current design to a Verilog file
write_verilog -noattr synth-example.v

The synthesis process involved several key steps:

1. Reading the Verilog Design: We started by reading the design file using the read_verilog command.
2. Mapping to the Internal Library: This was achieved using the techmap command.
3. Mapping Sequential Logic: The dfflibmap command was used to map the sequential logic to flip-flops.
4. Optimizing the Design: We used the abc -liberty command to map the combinational logic and optimize it according to the target library.
5. Cleaning Up: Any unused wires or cells were removed using the clean command.
6. Exporting the Netlist: Finally, the synthesized netlist was exported in Verilog format using the write_verilog command.

Command sequence in Yosys:

read_verilog top.v
synth -top top
dfflibmap -liberty /path/to/library.lib
abc -liberty /path/to/library.lib
clean
write_verilog top_synth.v

Executing TCL Command in Yosys:

Running Yosys

Check for synth_example.v (Netlist file) in the directory:

synth-example.v

Check the contents of Netlist file created after Synthesis:

Generated Netlist

Our exploration of Yosys provided invaluable insights into the synthesis process, from RTL to the final netlist. The flexibility and power of Yosys make it an excellent tool for both learning and professional design work in VLSI. Whether you’re a student, researcher, or industry professional, understanding tools like Yosys is essential for staying ahead in the field of digital design.