Understanding Delay Calculation and Static Timing Analysis Using OpenSTA: A Comprehensive Tutorial

7 min readSep 8, 2024

Introduction

In the field of VLSI design, precision and performance are key drivers of success. As the complexity of circuits grows, so does the need for accurate delay calculations and thorough Static Timing Analysis (STA). This tutorial is aimed at understanding the delay calculation and STA process, focusing on how technology libraries and constraints influence these processes. The open-source tool OpenSTA will be used for this purpose.

Prerequisites

Before diving into the tutorial, ensure you have the necessary tools and files set up:

OpenSTA: For those unfamiliar with OpenSTA, please refer to A Step-by-Step Guide to Installing and Running OpenSTA in a Docker Environment for Static Timing Analysis Tutorial for installation instructions.

Required files:

Design file: test.v

module top(a, out);
  input a;
  output out;
  INV I1 ( .I(a), .ZN(out)); 
endmodule

OpenSTA script file: test.tcl

read_liberty NangateOpenCellLibrary_typical.lib
read_verilog test.v
link_design top
read_sdc test.sdc
report_checks

SDC file: test.sdc

create_clock -name CLK -period 1000
set_input_delay 5 -clock CLK [get_ports a] 
set_output_delay 5 -clock CLK [get_ports out] 

set_input_transition 0.1 [get_ports a]
set_load 100 [get_ports out]


#set_input_transition 100 [get_ports a]

#set_load 0.1 [get_ports out]

#set_input_delay 25 -clock CLK [get_ports a] 

#set_output_delay 35 -clock CLK [get_ports out] 

#set_clock_uncertainty 100 CLK

Technology library: NangateOpenCellLibrary_typical.lib

https://github.com/The-OpenROAD-Project/alpha-release/blob/master/flow/platforms/nangate45/NangateOpenCellLibrary_typical.lib

Key Concepts

1. Non-Linear Delay Model (NLDM)

The NLDM is a widely-used approach for capturing the delay characteristics of a design. It is typically provided by the technology library and plays a crucial role in determining how delays are computed in a given circuit.

2. Constraints Overview

The success of static timing analysis depends on accurately defining various timing constraints:

create_clock: Defines a clock reference for timing analysis. This command ensures the analysis is performed relative to a specific clock signal.
set_input_delay: Specifies the delay at the input of the circuit, ensuring the timing analysis takes into account external delays.
set_output_delay: Models the delay requirements due to external components or circuits.
set_input_transition: Defines the transition or slew rate at the input, which impacts how quickly signals can change within the circuit.
set_load: Specifies the output load capacitance, which affects the overall delay.
set_clock_uncertainty: Adds pessimism into the analysis by factoring in uncertainties in the clock’s behavior, providing a more conservative estimate of timing.

Running the Experiment

Setting up OpenSTA Once you have installed OpenSTA (refer to A Step-by-Step Guide to Installing and Running OpenSTA in a Docker Environment for Static Timing Analysis Tutorial for guidance), you are ready to perform the timing analysis. Make sure you have all the required files in place:

test.v (design file)
test.tcl (OpenSTA script)
test.sdc (SDC file with constraints)
NangateOpenCellLibrary_typical.lib (technology library)

Performing the Analysis Run OpenSTA using the following steps:

Use the provided TCL script (test.tcl) to load the design, library, and constraints.
Execute the analysis and observe how the defined constraints (clock, input delays, output delays, and transitions) impact the STA process.

Analyzing the Results From the analysis, examine the expected delay values. For example, with the provided NangateOpenCellLibrary_typical.lib and sample designs such as small.v and small.sdc, you should expect a delay of 80 ps. By manipulating different constraints, you can observe how the delay changes.

Understanding the Impact

The key takeaway from this experiment is understanding how delays are influenced by external factors such as:

The technology library used (in this case, NangateOpenCellLibrary_typical.lib).
Various constraints like input delays, output delays, and transitions, which simulate real-world circuit behavior.
Clock-related uncertainties, which add an extra layer of complexity in timing closure.

When performing Static Timing Analysis (STA) using tools like OpenSTA, it’s essential to understand how each step in the timing flow affects your design. Each stage requires modifications to the TCL script that drive the analysis process. In this post, we’ll walk through how you can update your TCL script at every step of the STA flow, ensuring accurate results.

Why Update the TCL Script at Every Stage?

The TCL script is your gateway to defining and controlling the timing analysis parameters. As you move through various stages of the analysis, like modifying input transitions or adding output delays, you need to reflect those changes in your script to account for the impact on timing.

By updating the TCL script at every stage, you:

Ensure accurate timing results for each scenario.
Gain insights into how specific parameters (such as load or clock uncertainty) affect overall delay.
Build a comprehensive understanding of the design’s timing profile.

1. Base Timing Setup

At the first stage, you need a simple script to load the design, define the clock, and perform a basic timing analysis.

source test.tcl
report_checks

This script sets the basic design environment and runs an initial check on the timing. No additional constraints are applied at this stage, providing a baseline for further modifications.

2. Adding Input Transition

As you move into more detailed analysis, the next step is to account for input transition.

set_input_transition 100 [get_ports a]
report_checks

To do this, you update the TCL script to set the input transition for port a. This reflects how slower or faster input signals can affect delay. Running the updated script will show how the inverter and other elements are impacted by the transition time.

3. Applying Output Load

Next, you’ll want to factor in output load to see its effect on timing.

set_load 0.1 [get_ports out]
report_checks

Update the TCL script to simulate a load capacitance at the output port. Running this updated script will allow the STA tool to calculate delays accounting for the additional load on the circuit.

4. Defining Input Delay

Input delay represents the delay at the input due to external components.

set_input_delay 25 -clock CLK [get_ports a]
report_checks

Update the TCL script to include an input delay relative to the clock. Updating the script in this way ensures the STA tool is aware of any delays coming into the circuit, allowing it to calculate more realistic timing results.

5. Applying Output Delay

Just like input delays, output delays represent the timing requirements of components downstream of the circuit.

set_output_delay 35 -clock CLK [get_ports out]
report_checks

Update the TCL script to reflect the output delay. Setting the output delay ensures that STA is considering the necessary time for signals to propagate to external components, giving a more complete view of timing performance.

6. Adding Clock Uncertainty

Finally, clock uncertainty accounts for any jitter or variations in clock signals. Update the TCL script to reflect this uncertainty.

set_clock_uncertainty 100 CLK
report_checks

Adding clock uncertainty represents real-world imperfections in clock distribution. Factoring in this uncertainty can help create a more robust design that meets timing requirements even under non-ideal conditions.

Always Update Your TCL Script

As a student working with STA, it’s crucial to update your TCL script at every stage. Each modification — whether it’s adjusting input transitions, adding delays, or accounting for clock uncertainty — affects the timing analysis. By updating the script and running the analysis again, you ensure that you’re always working with the most accurate timing profile for your design.

This iterative process not only helps optimize timing but also gives you deeper insights into how real-world factors influence circuit performance. So, always keep your TCL script updated as you move through different stages of analysis!

By updating your TCL script at every stage, you maintain an accurate and dynamic view of your design’s timing, allowing you to optimize and verify that your circuit meets the necessary performance standards.

In this experiment, I’ve shown how each stage of the timing analysis was carried out using different library files. Each library introduces its unique set of delay models, which, when combined with varying input transitions, output loads, and clock uncertainties, can drastically impact the overall delay and slack in your design.

Conclusion

Static Timing Analysis is an essential part of VLSI design that ensures circuits meet the required performance targets. Using OpenSTA, designers can analyze and optimize delays, ensuring that their designs meet the timing requirements. Understanding how technology libraries and constraints affect these analyses will empower you to make more informed design decisions, improving both the efficiency and accuracy of your VLSI designs.

This tutorial serves as an introduction to the basics of delay calculation and STA, but further exploration of the OpenSTA tool will provide deeper insights into optimizing complex designs.